1. Field of the Invention
The present invention relates to a multi-layer printed circuit board. This application is based on Japanese Patent application No. 2006-347849, the disclosure of which is incorporated herein by reference.
2. Description of Related Art
In recent years, the package shape of a semiconductor device (hereafter, to be referred to as a logic part) for controlling a storage unit such as a memory is changed from a lead type to a CSP (Chip Size Package) type in which power source pins, ground pins and input/output pins can be arranged in a high density. At the same time, the increase in the number of the pins in the package is advanced, and restriction on pattern design of the printed circuit board on which the package is mounted is also increased.
FIGS. 1 to 3 show the outer appearance of a logic part. FIG. 1 is a top view of the logic part, FIG. 2 is a side view, and FIG. 3 is a view showing the rear side of the logic part. As shown in FIG. 3, many terminals are arranged on the rear side of the logic part. It should be noted that in FIG. 3, terminals for power sources and ground pins are shown inside the dashed line.
The configuration of the printed circuit board for mounting the above logic part will be described below with reference to FIGS. 4 to 8. In FIGS. 5 to 8, an inter-layer connection component 1 for the connection between wiring layers, a conductor pattern 2, and a mounting pad of the logic part are shown in FIGS. 5 to 8. FIG. 4 shows a part mounting surface of the printed circuit board, FIG. 5 shows a rear surface thereof, and FIGS. 6 and 7 show the inner wiring layers, respectively. FIG. 8 is an expanded view of a portion of the part mounting surface.
As shown in FIG. 4, a large number of mounting pads 3 for mounting the logic part are provided on the part mounting surface in correspondence to terminals on the rear surface of the logic part. Conductors for signal lines are connected to the respective mounting pads 3. Here, a conductor pattern 2 extending on the part-mounting surface is connected to the mounting pad 3 arranged on the relatively outer section side.
On the other hand, by a wiring only on the part mounting surface, the signal line cannot be connected to the mounting pad 3 arranged on the central section side among the mounting pads 3. This is because a space between the mounting pads 3 is occupied by the conductor patterns 2 extending for the mounting pads 3 on the relatively outer section side. Thus, an inter-layer connection component 1 is arranged to connect the mounting pad 3 on the central section side. That is, as shown in FIGS. 6 and 7, in the inner layer, the conductor pattern 2 as the signal line is extended to the central section and connected through the inter-layer connection component 1 to the mounting pad 3 on the part mounting surface.
As the above-mentioned inter-layer connection component 1, there are known a through-hole penetrating from the front to the rear of the board, a lead insertion hole described in a first conventional example (Japanese Laid Open Patent Application (JP-P2000-4086A)) and a via-holes described in a second conventional example (Japanese Laid Open Patent Application (JP-A-Heisei, 10-322027)).
If the via-hole and the lead insertion hole are used as the inter-layer connection components 1, it is possible to selectively connect a segment between the wiring layers. However, they require the manufacturing steps whose number is greater than that of the through-hole. Thus, in a memory mounting printed circuit board, the penetration through-holes have been used as the inter-layer connection components.
In association with the increase in the number of pins in the logic part, wiring layers in the printed circuit board trend to be increased. As a specific example, when a wiring rule is considered in which one conductive pattern is arranged between the penetration through-holes, one wiring layer is required to be added to the printed circuit board each time the terminals of the logic part are increased for one line. FIGS. 6 and 7 show such states. The increase in the wiring layer causes severe restriction on the printed circuit board design for a memory module. In the printed circuit board for the memory module, since the current form factors such as a socket are used, it is difficult to change the thickness of the printed circuit board. That is, the number of the layers must be increased without any change in the total thickness of the printed circuit board, and the thickness for one layer must be made thin. However, in case of the trial to make the thickness of each layer thin, a limit is in the process of manufacturing a fine structure of a conductor wiring and a constraint is from the viewpoint of the characteristic impedance of the wiring. Specifically, in the current memory module printed circuit board, it is difficult to exceed the 10 layers.
Also, the increase in the number of pins in the logic part is required to be attained without any increase in the impedances of a power source wiring and a ground wiring on the printed circuit board. Anti-pads 5 to protect a short-circuit are required to be arranged at the positions corresponding to the penetration through-holes in all of the power source and ground layers in the printed circuit board. FIG. 9 is a diagram showing the anti-pad 5. In FIG. 9, the inter-layer connection component 1, a conductor 6, and a space 4 to prevent the short-circuit are shown.
FIG. 10 shows a design example of the power source layer and ground layer in the board design shown in FIGS. 4 to 8. As shown in FIG. 10, a power source and ground area 6 is removed by the anti-pads 5. That is, the power source and ground area is removed, resulting in the increase in the impedances of the power source and ground wirings in the printed circuit board.
Therefore, the printed circuit board is demanded in which the number of pins in the logic part can be increased while suppressing the increase in the impedances of the power source and the ground wiring.
Also, in the memory module, the memories and the logic parts must be efficiently mounted on the printed circuit board. Thus, parts for decreasing the impedances of the power source and the ground wirings can be efficiently mounted on the opposite side to the logic parts, FIGS. 11 and 12 show this situation.
FIG. 11 shows an example in which a typical logic part 8 and impedance decreasing parts 9 (9a to 9e) such as a chip capacitor are mounted on a printed circuit board 7, and FIG. 12 shows an example in which the logic part 8 for the memory module, the memories 10a and 10b and an impedance decreasing part 9 are mounted on a printed circuit board 7. As shown in FIG. 11, in case of a typical module, many impedance decreasing parts 9 can be mounted on the printed circuit board 7 on the side opposite to the logic part 8. On the contrary, in case of the memory module shown in FIG. 12, the memories 10 must be mounted on the printed circuit board 7 on the side opposite to the logic part 8. Accordingly, the number of the mountable impedance decreasing parts 9 is extremely reduced. Thus, in the printed circuit board on which the memories are mounted, it is difficult to desirably decrease the impedance. That is, in particular, in the printed circuit board on which the memories are mounted, a technique is demanded that the increase of the impedance can be suppressed.